| Project Settings |
|---|
| Project Name | proj_1 | Device Name | impl_1: Lattice LFCPNX : LFCPNX_100 |
| Implementation Name | impl_1 | Top Module | presubmult |
| Pipelining | 1 | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 1000 |
| Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0 |
| Clock Conversion | 0 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
73 |
8 |
0 |
- |
00m:02s |
- |
2023-12-27
9:21 AM |
| (premap) | Complete |
5 |
0 |
0 |
0m:00s |
0m:01s |
198MB |
2023-12-27
9:21 AM |
| (fpga_mapper) | Complete |
9 |
1 |
0 |
0m:04s |
0m:08s |
227MB |
2023-12-27
9:21 AM |
| Multi-srs Generator |
Complete | | | | | | | 2023-12-27
9:21 AM |
| Area Summary |
|---|
|
| Register bits | 0 |
I/O cells | 79 |
| Block RAMs
(v_ram) | 0 |
DSPs
(dsp_used) | 1 |
| LUTs
(total_luts) | 0 |
| |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| clk | 200.0 MHz | NA | NA |
| System | 200.0 MHz | NA | NA |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 1 / 0 |
| |
|